VHDL formatter

VHDL is an established hardware description language used in specialized digital design domains, particularly where reliability and determinism are essential. Despite its continued use, tooling support for VHDL remains limited compared with many other programming languages. In particular, there is no formatter that enables consistent coding conventions or seamless integration into automated development workflows.

This project introduces a standalone command-line formatter for VHDL, based on a structured parsing and pretty-printing pipeline. ANTLR is used as the parser generator, providing a CST derived from the publicly available antlr grammar for VHDL. The CST is translated into an AST. This representation avoids the complexity of full semantic analysis with a focus on providing everything necessary for deterministic formatting.

The final output is produced using a document-based pretty printing strategy inspired by Philip Wadler's layout algebra. This method models formatting as the composition of layout primitives, such as indentation, line breaks and groups. To guarantee safety, the system implements a rigorous post-formatting
verification layer that compares the semantic token streams of the input and output, ensuring that the code's logic is preserved bit-for-bit. As a result, the formatter produces consistent and structurally clean code, independent of the quality of the input.

Recognizing the diversity of VHDL styles, the formatter is designed to be configurable. This allows users to define project-specific rules for indentation, keyword casing, and alignment strategies, ensuring the tool supports existing organizational style guides rather than enforcing a single fixed standard.

While full VHDL-2008 support is still in progress, the formatter already handles a substantial subset of the language. Future work aims to provide cross-platform binaries and editor integration to support streamlined and maintainable VHDL development.